The present invention relates to a method for producing a semiconductor device, and is usable for producing, for example, a semiconductor device having a nonvolatile memory.
As an electrically writable/erasable nonvolatile semiconductor memorizing unit, an EEPROM (electrically erasable and programmable read only memory) is widely used. Such a memorizing unit is a unit having a conductive floating gate electrode surrounded by an oxide film, or a trapping insulating film below a gate electrode of a MISFET, and is a unit in which a charge accumulating state in the floating gate or the trapping insulating film (charge holding part) is used as a memory data, and the data is read as a threshold of the transistor.
The trapping insulating film is an insulating film in which a charge can be accumulated. An example thereof is a silicon nitride film. By injecting a charge into such a charge accumulating region and discharging the charge therefrom, the threshold of the MISFET is shifted, thereby causing the MISFET to act as a memorizing element. An example of the trapping-insulating-film-used nonvolatile semiconductor memorizing unit is a split gate type cell using a MONOS (metal oxide nitride oxide semiconductor) film.
Patent Literature 1 (Japanese Unexamined Patent Application Publication No. 2009-302269) states that in a split gate type MONOS memory, a dummy ONO (oxide nitride oxide) film and a dummy memory gate electrode are formed, and thereafter ions are implanted into the workpiece to form source/drain regions and subsequently a memory gate electrode and an ONO film are re-formed into the workpiece.
In a process for producing split gate type MONOS memories, in the case of implanting ions into their workpiece across their memory gate electrodes in a non-crystalline state in order to form diffusion regions of their source/drain regions, the following problem is caused: when the ion implantation introduces an impurity into the non-crystalline state memory gate electrodes and then the memory gate electrodes are crystallized, crystal grains configured as the respective memory gate electrodes are varied in shape between these electrodes, so that properties of the memory cells may be unfavorably varied between the electrodes. Moreover, the impurity ions are implanted across the memory gate electrodes into an ONO film of the cells which includes a trapping insulating film, so that the cells are deteriorated in charge holding property and others.
In order to prevent these problems, known is a method of performing the following steps in turn: the steps of forming dummy memory gate electrodes in the workpiece; implanting ions thereinto for forming diffusion regions; removing the dummy memory gate electrodes; and forming memory gate electrodes and an ONTO film again.
However, when the dummy memory gate electrodes and the memory gate electrodes are formed to have substantially the same gate length, problems are caused that it is difficult to form LDD (lightly doped drain) structures, and further the memory cells are deteriorated in cut-off characteristic when not operated.
Other problems, and other novel features of the present invention will be made evident from the description of the present specification, and the attached drawings.